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[X86][Atom] Fix (U)COMISS/SD uops, latency and throughput
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Sat, 18 Sep 2021 20:29:33 +0000 (21:29 +0100)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Sun, 19 Sep 2021 11:44:44 +0000 (12:44 +0100)
commite381d8b24329cae6408205f74d0d6d9eaa6b29cf
treea466346c02496bdfdd07fabc9a94d6fe7ab14cd6tree | snapshot
parentb7ec8f3dcbcdf6d27902688c8eac0e6196061cb3commit | diff
[X86][Atom] Fix (U)COMISS/SD uops, latency and throughput

Both ports are required, for reg and mem variants - we can also use the WriteFComX class directly and remove the unnecessary InstRW overrides. Matches what Intel AoM / Agner / InstLatX64 report as well.
llvm/lib/Target/X86/X86ScheduleAtom.td diff | blob | history
llvm/test/tools/llvm-mca/X86/Atom/resources-sse1.s diff | blob | history
llvm/test/tools/llvm-mca/X86/Atom/resources-sse2.s diff | blob | history
Domain: System / Toolchain;