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armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3
authorPankit Garg <pankit.garg@nxp.com>
Mon, 5 Nov 2018 18:01:28 +0000 (18:01 +0000)
committerYork Sun <york.sun@nxp.com>
Thu, 6 Dec 2018 22:37:19 +0000 (14:37 -0800)
commite3506480466084a09d9882d546c3c3c677b13962
treed374b45dc79681b2a7068ca9ff74590292c1aeddtree | snapshot
parentbb50569dc4c3ac71af075d5e994d0a37579efc51commit | diff
armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3

Change tlb base address from OCRAM to DDR when exception level is
less than 3.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/cpu.c diff | blob | history
Domain: System / Kernel;