iommu/qcom: Add support for QSMMUv2 and QSMMU-500 secured contexts
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Thu, 22 Jun 2023 09:27:42 +0000 (11:27 +0200)
committerWill Deacon <will@kernel.org>
Wed, 9 Aug 2023 11:49:21 +0000 (12:49 +0100)
commite30c960d3f44b7aaa0861ce4afa8ba8b8f4b0f03
treec659eb4a4f61e8d09fa5de1294542fc2f014448c
parentec5601661bfcdc206e6ceba1b97837e763dab1ba
iommu/qcom: Add support for QSMMUv2 and QSMMU-500 secured contexts

On some SoCs like MSM8956, MSM8976 and others, secure contexts are
also secured: these get programmed by the bootloader or TZ (as usual)
but their "interesting" registers are locked out by the hypervisor,
disallowing direct register writes from Linux and, in many cases,
completely disallowing the reprogramming of TTBR, TCR, MAIR and other
registers including, but not limited to, resetting contexts.
This is referred downstream as a "v2" IOMMU but this is effectively
a "v2 firmware configuration" instead.

Luckily, the described behavior of version 2 is effective only on
secure contexts and not on non-secure ones: add support for that,
finally getting a completely working IOMMU on at least MSM8956/76.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
[Marijn: Rebased over next-20221111]
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622092742.74819-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Will Deacon <will@kernel.org>
drivers/iommu/arm/arm-smmu/qcom_iommu.c