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(parent: 69d757c) | patch
[llvm][aarch64] SVE addressing modes.
authorFrancesco Petrogalli <francesco.petrogalli@arm.com>
Tue, 28 Jan 2020 20:37:52 +0000 (20:37 +0000)
committerFrancesco Petrogalli <francesco.petrogalli@arm.com>
Fri, 21 Feb 2020 20:02:34 +0000 (20:02 +0000)
commite2ed1d14d6c2d11d1a5df23bd679bcb7e6cbf433
tree055b71c73d3c9bdad81c572562273882c3496538tree | snapshot
parent69d757c0e8ffc5b49fda10df38e470a56d616ef4commit | diff
[llvm][aarch64] SVE addressing modes.

Summary:
Added register + immediate and register + register addressing modes for the following intrinsics:

1. Masked load and stores:
     * Sign and zero extended load and truncated stores.
     * No extension or truncation.
2. Masked non-temporal load and store.

Reviewers: andwar, efriedma

Subscribers: cameron.mcinally, sdesmalen, tschuett, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74254
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td diff | blob | history
llvm/lib/Target/AArch64/SVEInstrFormats.td diff | blob | history
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-reg.ll [new file with mode: 0644] blob
Domain: System / Toolchain;