sbc8548: Fix up local bus init to be frequency aware
authorPaul Gortmaker <paul.gortmaker@windriver.com>
Sat, 31 Dec 2011 04:53:13 +0000 (23:53 -0500)
committerKumar Gala <galak@kernel.crashing.org>
Wed, 11 Jan 2012 19:59:17 +0000 (13:59 -0600)
commite2b363ff534ad943794682c60adf9cab6e3d3192
tree91adb318bbeecdcc61a27b9b37f8b90b2a38b73d
parent3e3262bd149e21d0f5a82648218c26f2aa0e15e7
sbc8548: Fix up local bus init to be frequency aware

The code here was copied from the mpc8548cds support, and it
wasn't using the CONFIG_SYS_LBC_LCRR define, and was just
unconditionally setting the LCRR_EADC bit.  Snooping with a
hardware debugger also showed we had LCRR_DBYP set, since we were
setting it based on a read of an uninitialized lcrr read via
clkdiv.  Borrow from the code in the tqm85xx.c support to add
LBC frequency aware masking of these bits.

This change will correct reliability issues associated with trying
to use the 128MB of LBC 100MHz SDRAM on this board.  Thanks to
Keith Savage for assistance in diagnosing the root cause of this.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
board/sbc8548/sbc8548.c