[ARM][LowOverheadLoops] Allow all MVE instrs.
authorSam Parker <sam.parker@arm.com>
Tue, 14 Jan 2020 12:02:32 +0000 (12:02 +0000)
committerSam Parker <sam.parker@arm.com>
Tue, 14 Jan 2020 12:03:58 +0000 (12:03 +0000)
commite27632c3026328e41b0d7dbf25631041e979a2f9
tree78681cb202d1b05ae6b5b3e7a63cc38a8e03f350
parent31aed2e0dad25d43039a9b933b1b95fbdeb27704
[ARM][LowOverheadLoops] Allow all MVE instrs.

We have a whitelist of instructions that we allow when tail
predicating, since these are trivial ones that we've deemed need no
special handling. Now change ARMLowOverheadLoops to allow the
non-trivial instructions if they're contained within a valid VPT
block. Since a valid block is one that is predicated upon the VCTP so
we know that these non-trivial instructions will still behave as
expected once the implicit predication is used instead.

This also fixes a previous test failure.

Differential Revision: https://reviews.llvm.org/D72509
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir [new file with mode: 0644]
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir [new file with mode: 0644]
llvm/unittests/Target/ARM/MachineInstrTest.cpp