[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
authorPhilipp Tomsich <philipp.tomsich@vrull.eu>
Wed, 8 Feb 2023 00:08:11 +0000 (01:08 +0100)
committerPhilipp Tomsich <philipp.tomsich@vrull.eu>
Wed, 8 Feb 2023 06:54:52 +0000 (07:54 +0100)
commite25b30d90a69846650fa15a3e41a013ea20193ff
tree213b5c9a1a9e430a5b798e00d760edf80e0819c2
parenta13645cf8c9ac403d4fa8da29a74392a4777b245
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension

The vendor-defined XTHeadBa (predating the standard Zba extension)
extension adds an address-generation instruction (th.addsl) with
similar semantics as sh[123]add from Zba.  It is supported by the C9xx
cores (e.g., found in the wild in the Allwinner D1) by Alibaba T-Head.

The current (as of this commit) public documentation for XTHeadBa is
available from:
  https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.2.2/xthead-2023-01-30-2.2.2.pdf

Support for these instructions has already landed in GNU Binutils:
  https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=8254c3d2c94ae5458095ea6c25446ba89134b9da

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D143029
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/rv32xtheadba.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rv64xtheadba.ll [new file with mode: 0644]
llvm/test/MC/RISCV/XTHeadBa-invalid.s [new file with mode: 0644]
llvm/test/MC/RISCV/XTHeadBa-valid.s [new file with mode: 0644]