Add support for RISC-V architecture.
authorNick Clifton <nickc@redhat.com>
Tue, 1 Nov 2016 16:45:57 +0000 (16:45 +0000)
committerNick Clifton <nickc@redhat.com>
Tue, 1 Nov 2016 16:45:57 +0000 (16:45 +0000)
commite23eba971dd409b999dd83d8df0f842680c1c642
tree0002ef536e33bff13648ee1f2c419349f4f91d75
parent4e56efac8b4d5e251e8edc13febec93992bd6eb4
Add support for RISC-V architecture.

bfd * Makefile.am: Add entries for riscv32-elf and riscv64-elf.
* config.bdf: Likewise.
* configure.ac: Likewise.
* Makefile.in: Regenerate.
* configure: Regenerate.
* archures.c: Add bfd_riscv_arch.
* reloc.c: Add riscv relocs.
* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
* bfd-in2.h: Regenerate.
* libbfd.h: Regenerate.
* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
* elfnn-riscv.c: New file.
* elfxx-riscv.c: New file.
* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
(get_machine_name): Likewise.
(dump_relocations): Add support for riscv relocations.
(get_machine_flags): Add support for riscv flags.
(is_32bit_abs_reloc): Add R_RISCV_32.
(is_64bit_abs_reloc): Add R_RISCV_64.
(is_none_reloc): Add R_RISCV_NONE.
* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
Expect the debug_ranges test to fail.

gas * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this architecture.
* configure.in: Define a default architecture.
* configure: Regenerate.
* configure.tgt: Add entries for riscv.
* doc/as.texinfo: Likewise.
* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
* config/tc-riscv.c: New file.
* config/tc-riscv.h: New file.
* doc/c-riscv.texi: New file.
* testsuite/gas/riscv: New directory.
* testsuite/gas/riscv/riscv.exp: New file.
* testsuite/gas/riscv/t_insns.d: New file.
* testsuite/gas/riscv/t_insns.s: New file.

ld * Makefile.am: Add riscv files.
* Makefile.in: Regenerate.
* NEWS: Mention the support for this target.
* configure.tgt: Add riscv entries.
* emulparams/elf32lriscv-defs.sh: New file.
* emulparams/elf32lriscv.sh: New file.
* emulparams/elf64lriscv-defs.sh: New file.
* emulparams/elf64lriscv.sh: New file.
* emultempl/riscvelf.em: New file.

opcodes * configure.ac: Add entry for bfd_riscv_arch.
* configure: Regenerate.
* disassemble.c (disassembler): Add support for riscv.
(disassembler_usage): Likewise.
* riscv-dis.c: New file.
* riscv-opc.c: New file.

include * dis-asm.h: Add prototypes for print_insn_riscv and
print_riscv_disassembler_options.
* elf/riscv.h: New file.
* opcode/riscv-opc.h: New file.
* opcode/riscv.h: New file.
56 files changed:
bfd/ChangeLog
bfd/Makefile.am
bfd/Makefile.in
bfd/archures.c
bfd/bfd-in2.h
bfd/config.bfd
bfd/configure
bfd/configure.ac
bfd/cpu-riscv.c [new file with mode: 0644]
bfd/elf-bfd.h
bfd/elfnn-riscv.c [new file with mode: 0644]
bfd/elfxx-riscv.c [new file with mode: 0644]
bfd/elfxx-riscv.h [new file with mode: 0644]
bfd/libbfd.h
bfd/reloc.c
bfd/targets.c
binutils/ChangeLog
binutils/readelf.c
binutils/testsuite/binutils-all/objdump.exp
gas/ChangeLog
gas/Makefile.am
gas/Makefile.in
gas/NEWS
gas/config/tc-riscv.c [new file with mode: 0644]
gas/config/tc-riscv.h [new file with mode: 0644]
gas/configure
gas/configure.ac
gas/configure.tgt
gas/doc/as.texinfo
gas/doc/c-riscv.texi [new file with mode: 0644]
gas/testsuite/gas/all/gas.exp
gas/testsuite/gas/elf/elf.exp
gas/testsuite/gas/riscv/riscv.exp [new file with mode: 0644]
gas/testsuite/gas/riscv/t_insns.d [new file with mode: 0644]
gas/testsuite/gas/riscv/t_insns.s [new file with mode: 0644]
include/ChangeLog
include/dis-asm.h
include/elf/riscv.h [new file with mode: 0644]
include/opcode/riscv-opc.h [new file with mode: 0644]
include/opcode/riscv.h [new file with mode: 0644]
ld/ChangeLog
ld/Makefile.am
ld/Makefile.in
ld/NEWS
ld/configure.tgt
ld/emulparams/elf32lriscv-defs.sh [new file with mode: 0644]
ld/emulparams/elf32lriscv.sh [new file with mode: 0644]
ld/emulparams/elf64lriscv-defs.sh [new file with mode: 0644]
ld/emulparams/elf64lriscv.sh [new file with mode: 0644]
ld/emultempl/riscvelf.em [new file with mode: 0644]
opcodes/ChangeLog
opcodes/configure
opcodes/configure.ac
opcodes/disassemble.c
opcodes/riscv-dis.c [new file with mode: 0644]
opcodes/riscv-opc.c [new file with mode: 0644]