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(parent: af16b95) | patch
[AMDGPU] fix readlane/readfirstlane src vgpr operand type.
authorValery Pykhtin <Valery.Pykhtin@amd.com>
Thu, 7 Apr 2016 13:41:51 +0000 (13:41 +0000)
committerValery Pykhtin <Valery.Pykhtin@amd.com>
Thu, 7 Apr 2016 13:41:51 +0000 (13:41 +0000)
commite23b6deb01e0e68734814ad48ab6de4980a8cd6b
treea0953e7b666b7426a3cc473b3b00556de54c4f8etree | snapshot
parentaf16b958c0a0746f3b3fc354443a6b16ff83a7eecommit | diff
[AMDGPU] fix readlane/readfirstlane src vgpr operand type.

For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand).
readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding).

Differential Revision: http://reviews.llvm.org/D18696

llvm-svn: 265670
llvm/lib/Target/AMDGPU/SIInstructions.td diff | blob | history
llvm/test/MC/Disassembler/AMDGPU/vop1_vi.txt diff | blob | history
llvm/test/MC/Disassembler/AMDGPU/vop2_vi.txt diff | blob | history
Domain: System / Toolchain;