[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)
authorVedant Kumar <vsk@apple.com>
Tue, 1 May 2018 19:51:15 +0000 (19:51 +0000)
committerVedant Kumar <vsk@apple.com>
Tue, 1 May 2018 19:51:15 +0000 (19:51 +0000)
commite23173b677c04329431703e1ae75ad2445de5e48
tree46ee39e97af771227b180a7f9dac62628c0b5ce1
parentd7117ed0f973371fb89a8647b92063c50562bd85
[DAGCombiner] Fix SDLoc in a (zext (zextload x)) combine (4/N)

The logic for this combine is almost identical to the logic for a
(sext (sextload x)) combine.

This commit factors out the logic so it can be shared by both combines,
and corrects the SDLoc assigned in the zext version of the combine.

Prior to this patch, for the given test case, we would apply the
location associated with the udiv instruction to instructions which
perform the load.

Part of: llvm.org/PR37262

llvm-svn: 331303
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/ARM/fold-zext-zextload.ll [new file with mode: 0644]
llvm/test/CodeGen/X86/h-registers-1.ll