drm/amd/display: Clean up for DCN1 clock debug logging
authorFatemeh Darbehani <fatemeh.darbehani@amd.com>
Tue, 30 Oct 2018 15:32:40 +0000 (11:32 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Nov 2018 17:04:45 +0000 (12:04 -0500)
commite2101675225fa45cf6994916c2051c5167ded3e2
treeffd16e734fcaef88debdaf7993e952e4155ac5e1
parente96938a09dce68356654186f4ac0a31837e1da6f
drm/amd/display: Clean up for DCN1 clock debug logging

[Why]
To prepare for clock debug logging. With the exception of removing
max_supported_dppclk_khz from logs, there are no functional changes.

[How]
Add clk_bypass struct and clean up buffer logic

Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Su Chung <Su.Chung@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_clk_mgr.h
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h