ppc4xx: Fix GPIO configuration for pcs440ep
authorStefan Roese <sr@denx.de>
Wed, 30 Jan 2008 14:35:50 +0000 (15:35 +0100)
committerStefan Roese <sr@denx.de>
Mon, 4 Feb 2008 10:47:40 +0000 (11:47 +0100)
commite1d1429b49b0ee58c80f8c7b29c1ebaf8be7f5f1
treeec68ac6e1f31bedb30d63d7a124cdf788eee89d4
parent28d77d968bfe0316deb5bf15c17f57d5ff2c8821
ppc4xx: Fix GPIO configuration for pcs440ep

The SRD0_PFC0 register was not configured correctly to enable the GPIO's
49-63 for GPIO. They have been configured as trace signals. This patch
fixes this by clearing the corresponding bit.

Signed-off-by: Stefan Roese <sr@denx.de>
board/pcs440ep/pcs440ep.c