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(parent: 7df5b3f) | patch
AMDGPU/GlobalISel: Select G_FABS/G_FNEG
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 10 Sep 2019 17:19:46 +0000 (17:19 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 10 Sep 2019 17:19:46 +0000 (17:19 +0000)
commite1895aba3da01df442253bf048e38371377db15e
treea961bae49e9391414f9c3596d13e1dbb8d93d65btree | snapshot
parent7df5b3fd26243a80d97382fdc09ce0374ab98d87commit | diff
AMDGPU/GlobalISel: Select G_FABS/G_FNEG

f64 doesn't work yet because tablegen currently doesn't handlde
REG_SEQUENCE.

This does regress some multi use VALU fneg cases since now the
immediate remains in an SGPR, and more moves are used for legalizing
the xor. This is a SIFixSGPRCopies deficiency.

llvm-svn: 371540
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIInstructions.td diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/fneg-combines.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/fneg.ll diff | blob | history
Domain: System / Toolchain;