AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 6 Feb 2020 21:11:45 +0000 (16:11 -0500)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 13 Feb 2020 00:19:45 +0000 (16:19 -0800)
commite174c278ca2f91bd2cae4fc849ba888fa7f851a9
tree5925e8b15403d7809076e4e32431eec37d62a3f8
parentde716173357f5715fe14788ec022e6eeb2b33540
AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result

When SI_IF is inserted, it constrains the source register with a
register class, which was quite likely a G_ICMP. This was incorrectly
treating it as a scalar, and then applyMappingImpl would end up
producing invalid MIR since this was unexpected.

Also fix not using all VGPR sources for vcc outputs.
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir