[ARM] Adjust AND immediates to make them cheaper to select.
authorEli Friedman <efriedma@codeaurora.org>
Fri, 10 Aug 2018 21:21:53 +0000 (21:21 +0000)
committerEli Friedman <efriedma@codeaurora.org>
Fri, 10 Aug 2018 21:21:53 +0000 (21:21 +0000)
commite1687a89e885c89b3a1f75c9ab35d5bb74a62869
treea91891b66373080d51e1374a1cdb031721482f44
parent29ec67b62f23e9dc357439809a01d6156e769eda
[ARM] Adjust AND immediates to make them cheaper to select.

LLVM normally prefers to minimize the number of bits set in an AND
immediate, but that doesn't always match the available ARM instructions.
In Thumb1 mode, prefer uxtb or uxth where possible; otherwise, prefer
a two-instruction sequence movs+ands or movs+bics.

Some potential improvements outlined in
ARMTargetLowering::targetShrinkDemandedConstant, but seems to work
pretty well already.

The ARMISelDAGToDAG fix ensures we don't generate an invalid UBFX
instruction due to a larger-than-expected mask. (It's orthogonal, in
some sense, but as far as I can tell it's either impossible or nearly
impossible to reproduce the bug without this change.)

According to my testing, this seems to consistently improve codesize by
a small amount by forming bic more often for ISD::AND with an immediate.

Differential Revision: https://reviews.llvm.org/D50030

llvm-svn: 339472
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.h
llvm/test/CodeGen/ARM/Windows/alloca.ll
llvm/test/CodeGen/ARM/Windows/vla.ll
llvm/test/CodeGen/ARM/and-cmpz.ll
llvm/test/CodeGen/ARM/illegal-bitfield-loadstore.ll
llvm/test/CodeGen/ARM/select_const.ll
llvm/test/CodeGen/Thumb/bic_imm.ll
llvm/test/CodeGen/Thumb/shift-and.ll