[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 24 Aug 2016 18:40:53 +0000 (18:40 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 24 Aug 2016 18:40:53 +0000 (18:40 +0000)
commite14653e17d33853c6f41609f0a69587f6f523d9c
treee253e973933e9c7ac410759b2c3b2d7b4843bc3e
parenta45c31a5b40ded42ad2cccc20f927f4e1ce7c125
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support

These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad

llvm-svn: 279652
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/test/CodeGen/X86/vec_ss_load_fold.ll