projects / platform / upstream / mesa.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 150b3e8) | patch
intel/compiler: Adjust CS payload registers for new register width on Xe2+
authorRohan Garg <rohan.garg@intel.com>
Fri, 22 Jul 2022 11:32:08 +0000 (13:32 +0200)
committerJordan Justen <jordan.l.justen@intel.com>
Thu, 21 Sep 2023 00:19:36 +0000 (17:19 -0700)
commite1289d613580a13c295686d464e84a422a09b60a
treeff18eeb57577db5cb8f3caa2d66208746ed80b56tree | snapshot
parent150b3e87c881a3ea8eb89f9d99290dbbdfdd3008commit | diff
intel/compiler: Adjust CS payload registers for new register width on Xe2+

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
src/intel/compiler/brw_fs_thread_payload.cpp diff | blob | history
Domain: Graphics System / GL;