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(parent: 0b063bd) | patch
drm/i915/gvt: Align render mmio list to cacheline
authorChangbin Du <changbin.du@intel.com>
Thu, 6 Apr 2017 02:55:02 +0000 (10:55 +0800)
committerZhenyu Wang <zhenyuw@linux.intel.com>
Wed, 12 Apr 2017 05:57:42 +0000 (13:57 +0800)
commite1236bc06c534a97f73e09aed5e1094108553e9f
tree16faf6807220b91820833a47fcc9818a93a46801tree | snapshot
parent0b063bd3ea9c13df78c82aa742e581c39f9d6156commit | diff
drm/i915/gvt: Align render mmio list to cacheline

Make the global mmio list be cacheline aligned to improve performance.

Signed-off-by: Changbin Du <changbin.du@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
drivers/gpu/drm/i915/gvt/render.c diff | blob | history
Domain: System / Kernel;