clk: qoriq: add clock configuration for ls1088a soc
authorYuantian Tang <andy.tang@nxp.com>
Thu, 6 Apr 2017 02:21:22 +0000 (10:21 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Fri, 21 Jul 2017 22:01:44 +0000 (15:01 -0700)
commite0c888c4a24dd4e55525f37ac854125b3e90c99a
tree3797ed33b87e614e22aa61c20ebc8b43cca24480
parent1f5e4c15d3bb298ed35b3b347fbd6112cd7a5d54
clk: qoriq: add clock configuration for ls1088a soc

Clock on ls1088a chip takes primary clocking input from the external
SYSCLK signal. The SYSCLK input (frequency) is multiplied using
multiple phase locked loops (PLL) to create a variety of frequencies
which can then be passed to a variety of internal logic, including
cores and peripheral IP modules.

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/clk-qoriq.c