[X86] Merge the different CMOV instructions for each condition code into single instr...
authorCraig Topper <craig.topper@intel.com>
Fri, 5 Apr 2019 19:27:41 +0000 (19:27 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 5 Apr 2019 19:27:41 +0000 (19:27 +0000)
commite0bfeb5f24979416144c16e8b99204f5f163b889
tree9fe1fba081f0d71c0f0f5c823e9a4115ef1eeb93
parent4af5d748ce34c3ef78b8b34c419508a58baafc60
[X86] Merge the different CMOV instructions for each condition code into single instructions that store the condition code as an immediate.

Summary:
Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models.

This avoids needing an isel pattern for each condition code. And it removes
translation switches for converting between CMOV instructions and condition
codes.

Now the printer, encoder and disassembler take care of converting the immediate.
We use InstAliases to handle the assembly matching. But we print using the
asm string in the instruction definition. The instruction itself is marked
IsCodeGenOnly=1 to hide it from the assembly parser.

This does complicate the scheduler models a little since we can't assign the
A and BE instructions to a separate class now.

I plan to make similar changes for SETcc and Jcc.

Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet

Reviewed By: RKSimon

Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60041

llvm-svn: 357800
40 files changed:
llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h
llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
llvm/lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp
llvm/lib/Target/X86/InstPrinter/X86InstPrinterCommon.h
llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
llvm/lib/Target/X86/X86CmovConversion.cpp
llvm/lib/Target/X86/X86FastISel.cpp
llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/lib/Target/X86/X86FrameLowering.cpp
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/lib/Target/X86/X86InstrCMovSetCC.td
llvm/lib/Target/X86/X86InstrCompiler.td
llvm/lib/Target/X86/X86InstrFoldTables.cpp
llvm/lib/Target/X86/X86InstrFormats.td
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstrInfo.h
llvm/lib/Target/X86/X86InstrInfo.td
llvm/lib/Target/X86/X86SchedBroadwell.td
llvm/lib/Target/X86/X86SchedHaswell.td
llvm/lib/Target/X86/X86SchedPredicates.td
llvm/lib/Target/X86/X86SchedSandyBridge.td
llvm/lib/Target/X86/X86SchedSkylakeClient.td
llvm/lib/Target/X86/X86SchedSkylakeServer.td
llvm/lib/Target/X86/X86Schedule.td
llvm/lib/Target/X86/X86ScheduleAtom.td
llvm/lib/Target/X86/X86ScheduleBdVer2.td
llvm/lib/Target/X86/X86ScheduleBtVer2.td
llvm/lib/Target/X86/X86ScheduleSLM.td
llvm/lib/Target/X86/X86ScheduleZnver1.td
llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
llvm/test/CodeGen/X86/flags-copy-lowering.mir
llvm/test/CodeGen/X86/non-value-mem-operand.mir
llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
llvm/test/CodeGen/X86/tail-call-conditional.mir
llvm/tools/llvm-exegesis/lib/X86/Target.cpp
llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
llvm/utils/TableGen/X86RecognizableInstr.cpp
llvm/utils/TableGen/X86RecognizableInstr.h