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(parent: 9dbe736) | patch
[NFC][RISCV] Remove redundant pseudo instructions for vector load/store.
authorHsiangkai Wang <kai.wang@sifive.com>
Fri, 29 Jan 2021 06:35:58 +0000 (14:35 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Fri, 29 Jan 2021 23:20:05 +0000 (07:20 +0800)
commite08b67f3a8ada62dcf84d41929c208adc656ba92
tree3604bb3315c58fdf003145b2a710eb53a8bd6f2ctree | snapshot
parent9dbe736cbd2c6a0c3d62a6fd6a2cf31c9ffc9577commit | diff
[NFC][RISCV] Remove redundant pseudo instructions for vector load/store.

Not all combinations of SEW and LMUL we need to support. For example, we
only need to support [M1, M2, M4, M8] for SEW = 64. There is no need to
define pseudos for PseudoVLSE64MF8, PseudoVLSE64MF4, and PseudoVLSE64MF2.

Differential Revision: https://reviews.llvm.org/D95667
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td diff | blob | history
Domain: System / Toolchain;