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(parent: ed9a56b) | patch
AMDGPU/GlobalISel: Fix extra result register in fdiv64 lowering
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Wed, 25 Dec 2019 12:48:37 +0000 (07:48 -0500)
committerMatt Arsenault <arsenm2@gmail.com>
Fri, 27 Dec 2019 13:49:43 +0000 (08:49 -0500)
commite088846712a6dfdc43328d4a81abb96452c0b456
treea8414d4507027aea0ca6ede0c781c187e3034b72tree | snapshot
parented9a56b0f2587fb14068a98f6dfa83c8f92105f5commit | diff
AMDGPU/GlobalISel: Fix extra result register in fdiv64 lowering

There ended up being two result registers, which would fail on
select. It was really defing a new temp register in the correct def
position, instead of the correct result register.
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir diff | blob | history
Domain: System / Toolchain;