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(parent: e1552f6) | patch
Add Support to Recognize and Vectorize NON SIMD instructions in SLPVectorizer.
authorKarthik Bhat <kv.bhat@samsung.com>
Fri, 20 Jun 2014 04:32:48 +0000 (04:32 +0000)
committerKarthik Bhat <kv.bhat@samsung.com>
Fri, 20 Jun 2014 04:32:48 +0000 (04:32 +0000)
commite03a25da70c6fd476d9be766eba0e46c9f3c1796
tree17758b552280556426b0a83160112b11ef9c3829tree | snapshot
parente1552f664861d9f60c21125f3ca042847c3d1b4acommit | diff
Add Support to Recognize and Vectorize NON SIMD instructions in SLPVectorizer.

This patch adds support to recognize patterns such as fadd,fsub,fadd,fsub.../add,sub,add,sub... and
vectorizes them as vector shuffles if they are profitable.
These patterns of vector shuffle can later be converted to instructions such as addsubpd etc on X86.
Thanks to Arnold and Hal for the reviews. http://reviews.llvm.org/D4015

llvm-svn: 211339
llvm/include/llvm/Analysis/TargetTransformInfo.h diff | blob | history
llvm/lib/CodeGen/BasicTargetTransformInfo.cpp diff | blob | history
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp diff | blob | history
llvm/lib/Target/X86/X86TargetTransformInfo.cpp diff | blob | history
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp diff | blob | history
llvm/test/Transforms/SLPVectorizer/X86/addsub.ll [new file with mode: 0644] blob
Domain: System / Toolchain;