kvm: x86: Set highest physical address bits in non-present/reserved SPTEs
authorJunaid Shahid <junaids@google.com>
Tue, 14 Aug 2018 17:15:34 +0000 (10:15 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sat, 15 Sep 2018 07:45:36 +0000 (09:45 +0200)
commite02c9275beea3b4990b61bdfb684da18aef3029c
tree2a7101fb71e874cd48543ec7baee3375d79e59d8
parent39cff99ba4692f8dc94b501d401cbd8b6ecaf1b2
kvm: x86: Set highest physical address bits in non-present/reserved SPTEs

commit 28a1f3ac1d0c8558ee4453d9634dad891a6e922e upstream.

Always set the 5 upper-most supported physical address bits to 1 for SPTEs
that are marked as non-present or reserved, to make them unusable for
L1TF attacks from the guest. Currently, this just applies to MMIO SPTEs.
(We do not need to mark PTEs that are completely 0 as physical page 0
is already reserved.)

This allows mitigation of L1TF without disabling hyper-threading by using
shadow paging mode instead of EPT.

Signed-off-by: Junaid Shahid <junaids@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/x86/kvm/mmu.c
arch/x86/kvm/x86.c