perf/x86/intel: Fix Skylake FRONTEND MSR extrareg mask
authorAndi Kleen <ak@linux.intel.com>
Wed, 9 Sep 2015 21:54:00 +0000 (14:54 -0700)
committerIngo Molnar <mingo@kernel.org>
Fri, 18 Sep 2015 07:20:23 +0000 (09:20 +0200)
commitdfe1f3cb312624928052413928d88b0ee3492216
tree8332940cc9097864e0dd142dd60bc2a84551d420
parentd0dc8494cd6904f8ad035d9ad97f313948f35d0c
perf/x86/intel: Fix Skylake FRONTEND MSR extrareg mask

Stephane pointed out that the extrareg mask was one bit too short.
The bubble width field was truncated by one bit. Fix that here.
Also add some extra comments on the reserved bits inside the event
select code.

Reported-by: Stephane Eranian <eranian@google.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1441835640-21347-3-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event_intel.c