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(parent: bd897a0) | patch
[AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions
authorScott Linder <scott@scottlinder.com>
Tue, 4 Sep 2018 21:50:47 +0000 (21:50 +0000)
committerScott Linder <scott@scottlinder.com>
Tue, 4 Sep 2018 21:50:47 +0000 (21:50 +0000)
commitdfe089dfd1e6ed1320730581392e14648a075cc2
treeed249ca6c35be14e26285926478b8e12a042d037tree | snapshot
parentbd897a02a0642b11eb3f5dbc6346e32c7fedce4dcommit | diff
[AMDGPU] Legalize VGPR Rsrc operands for MUBUF instructions

Emit a waterfall loop in the general case for a potentially-divergent Rsrc
operand. When practical, avoid this by using Addr64 instructions.

Differential Revision: https://reviews.llvm.org/D50982

llvm-svn: 341413
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIInstrInfo.h diff | blob | history
llvm/lib/Target/AMDGPU/SIInstrInfo.td diff | blob | history
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.mir [new file with mode: 0644] blob
Domain: System / Toolchain;