drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence
authorSatheeshakrishna M <satheeshakrishna.m@intel.com>
Fri, 22 Aug 2014 04:19:09 +0000 (09:49 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 16 Apr 2015 09:29:06 +0000 (11:29 +0200)
commitdfb82408471ee2e56b26c05dcd50317f873bee57
treed0c53fb958d47bddb3bd0222edba620a2dc51c66
parentff6d9f55fe3f217dabce6b5ee7dbd306be5f4391
drm/i915/bxt: Define bxt DDI PLLs and implement enable/disable sequence

Plug bxt PLL code into existing shared DPLL framework.

v2: (imre)
- squash in Satheeshakrishna's "Define BXT clock registers" and
  "Add state variables for bxt clock registers" patches
- squash in Vandanas's "Change grp access to lane access for PLL"
- fix group vs. lane access in bxt_ddi_pll_get_hw_state
- add code comment why we read from lane registers while writing to
  group registers
- clean up register macros
- use BXT_PORT_PLL_* macros instead of open-coding the same
- check if BXT_PORT_PCS_DW12_LN01 matches BXT_PORT_PCS_DW12_LN23
  during hardware state readout
- add missing LANESTAGGER_STRAP_OVRD masking
- add note about missing step according to the latest BUN for
  PORT_PLL_9/lockthresh

Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v1)
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ddi.c