[X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immedia...
authorCraig Topper <craig.topper@intel.com>
Tue, 13 Feb 2018 04:19:26 +0000 (04:19 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 13 Feb 2018 04:19:26 +0000 (04:19 +0000)
commitdf99baa4df985cfd9a1517b4ca79b41c179f4773
tree101c7543d69bf83420a46a2d7a371113bad0e9ef
parent4b89cc1b96682a14c6f95cf431cb946bc3f62e0c
[X86] Teach EVEX->VEX pass to turn VRNDSCALE into VROUND when bits 7:4 of the immediate are 0 and the regular EVEX->VEX checks pass.

Bits 7:4 control the scale part of the operation. If the scale is 0 the behavior is equivalent to VROUND.

Fixes PR36246

llvm-svn: 324985
12 files changed:
llvm/lib/Target/X86/X86EvexToVex.cpp
llvm/test/CodeGen/X86/avx-intrinsics-x86.ll
llvm/test/CodeGen/X86/avx-schedule.ll
llvm/test/CodeGen/X86/avx512-intrinsics.ll
llvm/test/CodeGen/X86/avx512-scalar.ll
llvm/test/CodeGen/X86/avx512vl-intrinsics.ll
llvm/test/CodeGen/X86/rounding-ops.ll
llvm/test/CodeGen/X86/sse41-intrinsics-x86.ll
llvm/test/CodeGen/X86/sse41-schedule.ll
llvm/test/CodeGen/X86/vec_floor.ll
llvm/test/CodeGen/X86/vec_ss_load_fold.ll
llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp