[IR] Increase max alignment to 4GB
authorArthur Eubanks <aeubanks@google.com>
Fri, 24 Sep 2021 22:54:17 +0000 (15:54 -0700)
committerArthur Eubanks <aeubanks@google.com>
Wed, 6 Oct 2021 16:54:14 +0000 (09:54 -0700)
commitdf84c1fe78130a86445d57563dea742e1b85156a
tree62faecab20072ce98f3701c2515488e3dc25af71
parentafdac5fbcb6a375245d435e4427086a376de59ff
[IR] Increase max alignment to 4GB

Currently the max alignment representable is 1GB, see D108661.
Setting the align of an object to 4GB is desirable in some cases to make sure the lower 32 bits are clear which can be used for some optimizations, e.g. https://crbug.com/1016945.

This uses an extra bit in instructions that carry an alignment. We can store 15 bits of "free" information, and with this change some instructions (e.g. AtomicCmpXchgInst) use 14 bits.
We can increase the max alignment representable above 4GB (up to 2^62) since we're only using 33 of the 64 values, but I've just limited it to 4GB for now.

The one place we have to update the bitcode format is for the alloca instruction. It stores its alignment into 5 bits of a 32 bit bitfield. I've added another field which is 8 bits and should be future proof for a while. For backward compatibility, we check if the old field has a value and use that, otherwise use the new field.

Updating clang's max allowed alignment will come in a future patch.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D110451
48 files changed:
clang/lib/CodeGen/CGBlocks.cpp
clang/lib/CodeGen/CGCall.cpp
clang/lib/CodeGen/CGDecl.cpp
clang/lib/CodeGen/CodeGenModule.cpp
llvm/include/llvm/Bitcode/BitcodeCommon.h
llvm/include/llvm/IR/DataLayout.h
llvm/include/llvm/IR/GlobalObject.h
llvm/include/llvm/IR/Instruction.h
llvm/include/llvm/IR/Instructions.h
llvm/include/llvm/IR/Value.h
llvm/include/llvm/Transforms/IPO/Attributor.h
llvm/lib/AsmParser/LLParser.cpp
llvm/lib/Bitcode/Reader/BitcodeReader.cpp
llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/SafeStack.cpp
llvm/lib/IR/DataLayout.cpp
llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
llvm/test/Assembler/align-inst-alloca.ll
llvm/test/Assembler/align-inst-load.ll
llvm/test/Assembler/align-inst-store.ll
llvm/test/Assembler/align-inst.ll
llvm/test/Bitcode/Inputs/invalid-align.bc
llvm/test/Bitcode/inalloca.ll
llvm/test/CodeGen/MIR/X86/load-with-max-alignment.mir [moved from llvm/test/CodeGen/MIR/X86/load-with-1gb-alignment.mir with 79% similarity]
llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead.ll
llvm/test/Transforms/Attributor/ArgumentPromotion/live_called_from_dead_2.ll
llvm/test/Transforms/Attributor/IPConstantProp/PR26044.ll
llvm/test/Transforms/Attributor/IPConstantProp/pthreads.ll
llvm/test/Transforms/Attributor/callbacks.ll
llvm/test/Transforms/Attributor/liveness.ll
llvm/test/Transforms/Attributor/memory_locations.ll
llvm/test/Transforms/Attributor/noalias.ll
llvm/test/Transforms/Attributor/nocapture-1.ll
llvm/test/Transforms/Attributor/noundef.ll
llvm/test/Transforms/Attributor/undefined_behavior.ll
llvm/test/Transforms/Attributor/value-simplify.ll
llvm/test/Transforms/GVN/PRE/2017-06-28-pre-load-dbgloc.ll
llvm/test/Transforms/InstCombine/atomic.ll
llvm/test/Transforms/InstCombine/getelementptr.ll
llvm/test/Transforms/InstCombine/load.ll
llvm/test/Transforms/InstCombine/mempcpy.ll
llvm/test/Transforms/InstCombine/pr44245.ll
llvm/test/Transforms/InstCombine/store.ll
llvm/test/Transforms/OpenMP/parallel_level_fold.ll
llvm/test/Verifier/align-md.ll
llvm/unittests/IR/ValueTest.cpp