[RISCV] Add ANDI to getRegAllocationHints.
authorCraig Topper <craig.topper@sifive.com>
Thu, 1 Dec 2022 04:54:27 +0000 (20:54 -0800)
committerCraig Topper <craig.topper@sifive.com>
Thu, 1 Dec 2022 04:59:02 +0000 (20:59 -0800)
commitdf7ab6a52e302b63837a34a15e3f35455fea2929
tree8c119b6670758598ea5f403feeba5b45ad5dc8bc
parent7899cc3c4536f31b9988165ebb5fb2c649b377f4
[RISCV] Add ANDI to getRegAllocationHints.
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/test/CodeGen/RISCV/bittest.ll
llvm/test/CodeGen/RISCV/branch.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
llvm/test/CodeGen/RISCV/setcc-logic.ll
llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
llvm/test/CodeGen/RISCV/urem-vector-lkk.ll