powerpc/mm: Add MMU features for TLB reservation & Paired MAS registers
authorKumar Gala <galak@kernel.crashing.org>
Mon, 24 Aug 2009 15:52:48 +0000 (15:52 +0000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 28 Aug 2009 04:24:12 +0000 (14:24 +1000)
commitdf5d6ecf8157245ef733db87597adb2c6e2510da
tree9b1df8a76713d55ca08d11bd212281b11f6af652
parent23e55f92d4fd733365dd572ea6e9e211387123c2
powerpc/mm: Add MMU features for TLB reservation & Paired MAS registers

Support for TLB reservation (or TLB Write Conditional) and Paired MAS
registers are optional for a processor implementation so we handle
them via MMU feature sections.

We currently only used paired MAS registers to access the full RPN + perm
bits that are kept in MAS7||MAS3.  We assume that if an implementation has
hardware page table at this time it also implements in TLB reservations.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/include/asm/mmu.h
arch/powerpc/mm/tlb_low_64e.S