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(parent: 51a41f2) | patch
[InstCombine] Optimize shl+lshr+and conversion pattern
authorchenglin.bi <chenglin.bi@cixcomputing.com>
Fri, 10 Jun 2022 01:36:58 +0000 (09:36 +0800)
committerchenglin.bi <chenglin.bi@cixcomputing.com>
Fri, 10 Jun 2022 01:36:58 +0000 (09:36 +0800)
commitde7a6ae1ffc36baa16188d3dd5befa385d05700d
treeb68b3e39eb887aab56d33e8cdd4f25edcf42667ftree | snapshot
parent51a41f23b62ce0afbf395a251d9662390b28440ccommit | diff
 [InstCombine] Optimize shl+lshr+and conversion pattern

if `C1` and `C3` are pow2 and `Log2(C3)+C2 < BitWidth`:
    ((C1 << X) >> C2) & C3 -> X == (Log2(C3)+C2-Log2(C1)) ? C3 : 0;

https://alive2.llvm.org/ce/z/Pus5bd

Fix issue https://github.com/llvm/llvm-project/issues/55739

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D126617
llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp diff | blob | history
llvm/test/Transforms/InstCombine/and.ll diff | blob | history
llvm/test/Transforms/InstCombine/icmp-and-shift.ll diff | blob | history
Domain: System / Toolchain;