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(parent: fa8967c) | patch
arm: socfpga: Restructure clock manager driver
authorLey Foon Tan <ley.foon.tan@intel.com>
Tue, 25 Apr 2017 18:44:33 +0000 (02:44 +0800)
committerMarek Vasut <marex@denx.de>
Thu, 18 May 2017 09:33:16 +0000 (11:33 +0200)
commitde7781158923a9c87debc5a89ce4fabfd0fc93bc
tree2f688d87f0559d5c19d48f633681abffd10d5f52tree | snapshot
parentfa8967cfbaed5582ba987756fa9f0470a9affbf4commit | diff
arm: socfpga: Restructure clock manager driver

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
  cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
arch/arm/mach-socfpga/Makefile diff | blob | history
arch/arm/mach-socfpga/clock_manager.c diff | blob | history
arch/arm/mach-socfpga/clock_manager_gen5.c [new file with mode: 0644] blob
arch/arm/mach-socfpga/include/mach/clock_manager.h diff | blob | history
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h [new file with mode: 0644] blob
arch/arm/mach-socfpga/spl.c diff | blob | history
Domain: System / Kernel;