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(parent: 1180ed4) | patch
[RISCV] Don't fold (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq...
authorCraig Topper <craig.topper@sifive.com>
Tue, 16 Aug 2022 21:08:38 +0000 (14:08 -0700)
committerCraig Topper <craig.topper@sifive.com>
Tue, 16 Aug 2022 21:11:31 +0000 (14:11 -0700)
commitde6fd169715764f0401d8580b64c11fda45101e1
tree2466937498af8be23e6740b08a1b66610fe6aaf4tree | snapshot
parent1180ed41ee9de1804ddbfee4e6306dd20d12cd2bcommit | diff
[RISCV] Don't fold (sub C, (setcc x, y, eq/neq)) -> (add C-1, (setcc x, y, neq/eq)) if C-1 isn't simm12.

We still need to materialize the constant in a register and we
may not be removing all uses of the original constant so it may
increase code size.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/select-const.ll diff | blob | history
Domain: System / Toolchain;