clk: g12a/g12b: fix syspll overflow when freq larger than 2.1g [1/1]
authorShunzhou Jiang <shunzhou.jiang@amlogic.com>
Fri, 22 Feb 2019 09:18:36 +0000 (17:18 +0800)
committerJianxin Pan <jianxin.pan@amlogic.com>
Tue, 26 Feb 2019 07:32:19 +0000 (23:32 -0800)
commitde458631bd3d82ed4a145d162b820b43b19aedb7
tree81ca43995f07540246b98bf63570c08e5d6f5544
parent29f98b3e7ea1bcaf18ad60f1023496d8de7843d3
clk: g12a/g12b: fix syspll overflow when freq larger than 2.1g [1/1]

PD#SWPL-5076

Problem:
syspll overflow

Solution:
div 1000 when round rate

Verify:
test pass on g12a skt/w400

Change-Id: I021a1e8fd1280b27e21e5b4c8983b91fb89e84ba
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
drivers/amlogic/clk/g12a/g12a_clk-pll.c