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[MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency
authorGuozhi Wei <carrot@google.com>
Tue, 28 Jun 2022 21:42:51 +0000 (21:42 +0000)
committerGuozhi Wei <carrot@google.com>
Tue, 28 Jun 2022 21:42:51 +0000 (21:42 +0000)
commitddc9e8861ccf8ac3cf45e9d8cda58bdb2b0be63b
treeba95035430506b2426f3c9a2fc5dc0bb9a05b135tree | snapshot
parent906f52f2c4fc4cedbe37d420cbd3031da0641d81commit | diff
[MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency

Add a new pattern A - (B + C) ==> (A - B) - C to give machine combiner a chance
to evaluate which instruction sequence has lower latency.

Differential Revision: https://reviews.llvm.org/D124564
llvm/include/llvm/CodeGen/MachineCombinerPattern.h diff | blob | history
llvm/lib/CodeGen/MachineCombiner.cpp diff | blob | history
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp diff | blob | history
llvm/test/CodeGen/AArch64/machine-combiner-subadd.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir [new file with mode: 0644] blob
Domain: System / Toolchain;