drm/radeon: fixes for gfx clockgating on CIK
authorAlex Deucher <alexander.deucher@amd.com>
Mon, 12 Aug 2013 21:25:26 +0000 (17:25 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 30 Aug 2013 20:30:55 +0000 (16:30 -0400)
commitddc76ff6c78ecb189102bdc3bd9d14de5b750a6f
treed143e2aa3f3e5eb3197f2a055bae2e4d3421b44c
parent473359bc28e193031a76d99f71e8b6c4808719a6
drm/radeon: fixes for gfx clockgating on CIK

Clockgating requires signalling between the CP and the
RLC to work properly.  Resetting the CP block in the
CP resume code messed up the internal coordination
between the blocks.  Removing the reset allows gfx
clockgating to work properly.  However, when gfx clock
gating is enabled, there is a strange interaction with
dpm which causes the chip to stay in the high performance
level all the time, so leave gfx clockgating disabled
for now.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/radeon/cik.c
drivers/gpu/drm/radeon/radeon_asic.c