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(parent: 8848474) | patch
riscv: ax25: Andes specific cache shall only support in M-mode
authorRick Chen <rick@andestech.com>
Tue, 2 Apr 2019 07:56:42 +0000 (15:56 +0800)
committerAndes <uboot@andestech.com>
Mon, 8 Apr 2019 01:45:08 +0000 (09:45 +0800)
commitdda00ae4ef357233a72c74e6c02d27b70c844422
tree53f9e29c4d779504b36dbee95bee7f1f44813f4atree | snapshot
parent8848474c5e9093ac27f6b7cc8be156629c7d0badcommit | diff
riscv: ax25: Andes specific cache shall only support in M-mode

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
arch/riscv/cpu/ax25/Kconfig diff | blob | history
Domain: System / Kernel;