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(parent: 6f46c74) | patch
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock
authorAswath Govindraju <a-govindraju@ti.com>
Fri, 28 Jan 2022 08:11:36 +0000 (13:41 +0530)
committerTom Rini <trini@konsulko.com>
Tue, 8 Feb 2022 16:00:03 +0000 (11:00 -0500)
commitdd75927059c51f1e1e9d443c8a3e78254ca2d4ab
treedff7f5464313f1fef0434104682d2ef76632baaftree | snapshot
parent6f46c7441a9f02133ae997238712819dab8c95eecommit | diff
phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock

Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
drivers/phy/cadence/phy-cadence-sierra.c diff | blob | history
Domain: System / Kernel;