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[AArch64] Combine ISD::SETCC into AArch64ISD::ANDS
authorchenglin.bi <chenglin.bi@cixcomputing.com>
Sat, 19 Mar 2022 12:54:44 +0000 (12:54 +0000)
committerPaul Walker <paul.walker@arm.com>
Sat, 19 Mar 2022 13:04:16 +0000 (13:04 +0000)
commitdd3b90e4d77b0cc874ffcaaeb28776ba0fd15032
tree1e7615a9cd95bc9f1dbaac400713c545e1249bebtree | snapshot
parentf46fe36d59f6592162f88af08bf04c6998afd636commit | diff
[AArch64] Combine ISD::SETCC into AArch64ISD::ANDS

When N > 12, (2^N -1) is not a legal add immediate (isLegalAddImmediate will return false).
ANd if SetCC input use this number, DAG combiner will generate one more SRL instruction.
So combine [setcc (srl x, imm), 0, ne] to [setcc (and x, (-1 << imm)), 0, ne] to get better optimization in emitComparison
Fix https://github.com/llvm/llvm-project/issues/54283

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D121449
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp diff | blob | history
llvm/test/CodeGen/AArch64/arm64-xaluo.ll diff | blob | history
Domain: System / Toolchain;