drm/i915/guc: Add Gen9 registers for GuC error state capture.
authorAlan Previn <alan.previn.teres.alexis@intel.com>
Mon, 21 Mar 2022 16:45:19 +0000 (09:45 -0700)
committerLucas De Marchi <lucas.demarchi@intel.com>
Tue, 22 Mar 2022 17:33:30 +0000 (10:33 -0700)
commitdce2bd5423374973f2a66d6e00e932eb0a5d32d6
tree8d1af183aa5b03d90f73308fe51ec681c00f2f1b
parent33a220f6fcfc7fd9819f96aac69356593a63b10f
drm/i915/guc: Add Gen9 registers for GuC error state capture.

Abstract out a Gen9 register list as the default for all other
platforms we don't yet formally support GuC submission on.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220321164527.2500062-6-alan.previn.teres.alexis@intel.com
drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c