[AArch64][GlobalISel] Fold away lowered vector sign-extend of vector compares.
authorAmara Emerson <amara@apple.com>
Mon, 3 Oct 2022 14:19:05 +0000 (15:19 +0100)
committerAmara Emerson <amara@apple.com>
Mon, 3 Oct 2022 20:39:53 +0000 (21:39 +0100)
commitdcd02a524befcec71f46ab76d725b2a8f8623d69
tree3c9201cc9c132430906efc1c2f90bd4663896efd
parent07ccf651b95b3d92904e5d513772ad51567d8334
[AArch64][GlobalISel] Fold away lowered vector sign-extend of vector compares.

This fixes a long standing cause of awful code generation when legalization creates
G_SEXT(G_FCMP(...)), for example due to promoting the condition of a vector G_SELECT.

Since on AArch64 vector compares sign-extend the condition value, there's no need
for this extra G_SEXT. Unfortunately by the time we get to post-legalization these
G_SEXTs have already been lowered into shifts, so this combine is a bit more
involved than I'd ideally like. Oh well.

Differential Revision: https://reviews.llvm.org/D135078
llvm/lib/Target/AArch64/AArch64Combine.td
llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll
llvm/test/CodeGen/AArch64/GlobalISel/postlegalizer-combiner-sext-of-vcmp.mir [new file with mode: 0644]
llvm/test/CodeGen/AArch64/arm64-vabs.ll
llvm/test/CodeGen/AArch64/min-max.ll
llvm/test/CodeGen/AArch64/neon-compare-instructions.ll