drm/i915: calculate the port clock rate along with other PLL params
authorImre Deak <imre.deak@intel.com>
Mon, 22 Jun 2015 20:35:51 +0000 (23:35 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Tue, 30 Jun 2015 10:35:32 +0000 (12:35 +0200)
commitdccbea3b0704c77c5bbd9e5e9240d6eb253d2565
tree4b61e2f7a5ff90a7731fe20d968d09d914a67f66
parent589eca678a0348687fbfc3194a0d87467a3f6c3f
drm/i915: calculate the port clock rate along with other PLL params

Depending on the platform the port clock fed to the pipe can be the PLL's
post-divided fast clock rate or a /5 divided version of it. To make this
more obvious across the platforms calculate this port clock along with
the rest of the PLL parameters.

This is also needed by the next patch where we can reuse the CHV helper
for the BXT PLL HW readout code; so export the corresponding helper.

While at it also add a more descriptive name to the helpers and a
comment explaining what's being calculated.

No functional change.

Suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_drv.h