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clk: samsung: exynos5420: Add pll_rate_table and clock id for EPLL
authorChanwoo Choi <cw00.choi@samsung.com>
Tue, 29 Dec 2015 01:42:39 +0000 (10:42 +0900)
committerSeung-Woo Kim <sw0312.kim@samsung.com>
Thu, 31 Mar 2016 07:59:40 +0000 (16:59 +0900)
commitdcc68c64592a40b9bb9bcc8b3ea5a087d9fb1276
treebe04e6e7cc1b5b892d239aee49dcc942502e43c7tree | snapshot
parent3ba353d4e6f3e9334872588a25a56469e0a537b5commit | diff
clk: samsung: exynos5420: Add pll_rate_table and clock id for EPLL

This patch add the clock id of EPLL to handle it on devicetree file
and the rate tables. EPLL is used as root clock of ASS (Audio Subsystem).

Change-Id: Iefcbd5ea4cb911a3b5d75888286926773a98af54
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
drivers/clk/samsung/clk-exynos5420.c diff | blob | history
include/dt-bindings/clock/exynos5420.h diff | blob | history
Domain: System / Kernel;