[IfCvt] Don't use pristine register for counting liveins for predicated instructions.
authorDavid Green <david.green@arm.com>
Sun, 11 Jul 2021 13:45:54 +0000 (14:45 +0100)
committerDavid Green <david.green@arm.com>
Sun, 11 Jul 2021 13:45:54 +0000 (14:45 +0100)
commitdc0bbc9d891ab20850761d8d75acc6676754ce2d
treea30aaa0a735dc34dcc04f03a4ed750ff0fc732cf
parent6062c672bc5e560a4c3dc73741f9e82b39d08527
[IfCvt] Don't use pristine register for counting liveins for predicated instructions.

The test case here hits machine verifier problems. There are volatile
long loads that the results of do not get used, loading into two dead
registers. IfCvt will predicate them and as it does will add implicit
uses of the predicating registers due to thinking they are live in. As
nothing has used the register, the machine verifier disagrees that they
are really live and we end up with a failure.

The registers come from Pristine regs that LivePhysRegs counts as live.
This patch adds a addLiveInsNoPristines method to be used instead in
IfCvt, so that only really live in regs need to be added as implicit
operands.

Differential Revision: https://reviews.llvm.org/D90965
llvm/include/llvm/CodeGen/LivePhysRegs.h
llvm/lib/CodeGen/IfConversion.cpp
llvm/lib/CodeGen/LivePhysRegs.cpp
llvm/test/CodeGen/ARM/ldrd_ifcvt.ll [new file with mode: 0644]