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(parent: 98dff5e) | patch
[RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.
authorCraig Topper <craig.topper@sifive.com>
Fri, 19 Feb 2021 18:00:13 +0000 (10:00 -0800)
committerCraig Topper <craig.topper@sifive.com>
Fri, 19 Feb 2021 18:07:12 +0000 (10:07 -0800)
commitdbf910f0d95011e9485af859a10efb75bf28ee89
tree56e92f01fe3ab177db8146828ee365c0b6ef459ftree | snapshot
parent98dff5e804229d1d2fc139e44e7a04fc06bb6f92commit | diff
[RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.

Just like we do for isel patterns, we need to call selectVLOp
to prevent 0 from being selected to X0 by the default isel.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D97021
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp diff | blob | history
llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll [new file with mode: 0644] blob
Domain: System / Toolchain;