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(parent: d625b4b) | patch
[AMDGPU] Add 192-bit register classes
authorJay Foad <jay.foad@amd.com>
Thu, 16 Apr 2020 16:02:19 +0000 (17:02 +0100)
committerJay Foad <jay.foad@amd.com>
Wed, 22 Apr 2020 12:10:37 +0000 (13:10 +0100)
commitdbdffe3ee9d6fd4739bef5f03e61f052a95e72ca
tree18fcd895c761d6265918e06a150e82b6aa8ea3c9tree | snapshot
parentd625b4b081f9ea2d96d5bdfc1f05925b30d8b1a3commit | diff
[AMDGPU] Add 192-bit register classes

Differential Revision: https://reviews.llvm.org/D78312
16 files changed:
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td diff | blob | history
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp diff | blob | history
llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/SIRegisterInfo.td diff | blob | history
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll [deleted file] blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/zextload-xfail.ll [deleted file] blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll diff | blob | history
llvm/test/CodeGen/AMDGPU/ipra-regmask.ll diff | blob | history
Domain: System / Toolchain;