[DAG] Do MergeConsecutiveStores again before Instruction Selection
authorNirav Dave <niravd@google.com>
Mon, 27 Nov 2017 15:28:15 +0000 (15:28 +0000)
committerNirav Dave <niravd@google.com>
Mon, 27 Nov 2017 15:28:15 +0000 (15:28 +0000)
commitdb77e57ea86d941a4262ef60261692f4cb6893e6
tree5ea93e1652b4f3065657d9618c69315582b377a4
parent948a915924ded9364ddf2d55ad69f47b37bc0843
[DAG] Do MergeConsecutiveStores again before Instruction Selection

Summary:

Now that store-merge is only generates type-safe stores, do a second
pass just before instruction selection to allow lowered intrinsics to
be merged as well.

Reviewers: jyknight, hfinkel, RKSimon, efriedma, rnk, jmolloy

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D33675

llvm-svn: 319036
13 files changed:
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/arm64-complex-ret.ll
llvm/test/CodeGen/AArch64/arm64-narrow-st-merge.ll
llvm/test/CodeGen/AArch64/arm64-variadic-aapcs.ll
llvm/test/CodeGen/AArch64/tailcall-explicit-sret.ll
llvm/test/CodeGen/AArch64/tailcall-implicit-sret.ll
llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
llvm/test/CodeGen/ARM/fp16-promote.ll
llvm/test/CodeGen/BPF/undef.ll
llvm/test/CodeGen/Mips/cconv/vector.ll
llvm/test/CodeGen/Mips/llvm-ir/extractelement.ll
llvm/test/CodeGen/SystemZ/fp-move-13.ll