[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.
authorHsiangkai Wang <kai.wang@sifive.com>
Fri, 11 Dec 2020 08:08:10 +0000 (16:08 +0800)
committerHsiangkai Wang <kai.wang@sifive.com>
Tue, 15 Dec 2020 12:15:06 +0000 (20:15 +0800)
commitdb48a6de7702570083c9b88f4721701b0f2dbfe1
tree0746303819a004e4aabd824d4fdad2d7d0b48971
parentb74c4dbb9634f6210c6539fb4c09b0b68cb3cf0a
[RISCV] Define vwadd/vwaddu/vwsub/vwsubu intrinsics.

Define vwadd/vwaddu/vwsub/vwsubu intrinsics and lower to V instructions.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Hsiangkai Wang <kai.wang@sifive.com>
Differential Revision: https://reviews.llvm.org/D93108
19 files changed:
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll [new file with mode: 0644]
llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll [new file with mode: 0644]