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author	Xingyu Wu <xingyu.wu@starfivetech.com>
	Mon, 15 Aug 2022 07:05:05 +0000 (15:05 +0800)
committer	Xingyu Wu <xingyu.wu@starfivetech.com>
	Fri, 19 Aug 2022 03:15:08 +0000 (11:15 +0800)
commit	db3fc924d7e25597d3160e51e7acf4020364f35a
tree	abf22700ac455652294f6b63a9377e811346d645	tree \| snapshot
parent	d0b7c0eb768754018893706f54ef3113195604c8	commit \| diff

clk:starfive:Modify 'stg_apb' clock

Change 'stg_apb' clock from external clock to
internal clock.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>

arch/riscv/boot/dts/starfive/jh7110-clk.dtsi	[changed mode: 0644->0755]	diff \| blob \| history
arch/riscv/boot/dts/starfive/jh7110.dtsi		diff \| blob \| history
drivers/clk/starfive/clk-starfive-jh7110-stg.c		diff \| blob \| history
include/dt-bindings/clock/starfive-jh7110-clkgen.h		diff \| blob \| history

Domain: System / Kernel;